Electrostatic discharge (ESD) refers to the phenomenon of electrical discharge of high current for a short time duration resulting from a build up of static charge on a particular integrated circuit package, or on a nearby human handling that particular IC package. ESD events can have serious detrimental effects on manufacture and performance of integrated circuits (ICs) and other microelectronic devices, systems that contain such devices and manufacturing facilities that produce them. Advances in silicon process technology have led to the development of increasingly smaller sizes for transistors in integrated circuits. In turn, the decreasing size of transistors has made the circuits increasingly susceptible to damage from ESD events.
As we enter the new millennium, the electronic industry continues to scale microelectronic structure to achieve faster devices, new devices, and more per unit area. ESD continues to be a threat for scaled structures produced using various new technologies used in the electronic industry, such as, submicron device technologies, high system operation speeds, higher levels of factory automation, etc. As integrated circuit devices increase in density and their operating supply voltages decrease, the integrated circuits become more sensitive to the effects of ESD. Especially, ESD is a serious problem for semiconductor devices since it has the potential to destroy an entire IC. Because ESD events occur often across the silicon circuits attached to IC package terminals, circuit designers have concentrated their efforts on developing adequate protection mechanisms for these sensitive circuits.
One solution is the use of a grounded gate transistor as a simple ESD protection circuit. The transistor is configured as a diode and has a drain junction breakdown voltage lower than the gate dielectric breakdown voltage. While this circuit provides some protection from ESD events, an ESD protection circuit should also be able to protect an IC against static discharge by non-destructively passing large currents through a low impedance path in a short time.
Electronic circuits known as power supply clamps have long served the function of protecting power rails during ESD events. FIG. 1 illustrates a block diagram of an exemplary integrated circuit which is well known to one of ordinary skill in the art. FIG. 1 shows an integrated circuit 10 which has a voltage supply input connection 12 for receiving an externally provided high supply voltage from supply circuit 14. An ESD protection circuit 16 is provided to protect internal circuitry 18, designed to perform a predetermined function, from an electrostatic discharge. The ESD protection circuit 16 is described in detail below. The integrated circuit 10 can be any type of integrated circuit which receives a supply voltage, including, but not limited to, processors, controllers, memory devices, application specific integrated circuits (ASIC), etc.
Because certain standardized or legacy supply voltages can be high enough to cause premature failure in metal-oxide semiconductor (MOS) devices used in integrated circuits, redesigned clamp circuits are needed to provide ESD protection to high voltage pins. Such circuits, known as voltage-tolerant clamps or multi-stack claims, are able to withstand high voltages by self-generating bias voltages that are low enough for MOS devices to attach to without causing damage.
A desirable bias voltage circuit should have the characteristics of low power consumption, strong current drive, and limited degradation of the ESD performance of the clamp. Low power consumption may be defined as being negligible compared to the overall power consumption of the clamp. Strong current drive must be measured by its ability to drive large loads while keeping the bias voltage on target. On the other hand, limited degradation of ESD performance should be proven by a negligible shift in the pulse current-voltage characteristics of the clamp under various operating conditions.
FIG. 2 illustrates an exemplary prior art implementation of a voltage tolerant clamp circuit 20. The clamp circuit 20 includes a voltage divider 22 formed by devices 24 and 26 between nodes 28 and 30, a controller circuit 32 including, among other devices, a device 34, and a current sinking device 36 having current sinking device transistors 38 and 40. The transistors 38 and 40 used by the current sinking device 36 may be any of the commonly used transistors. For example, the transistors 38 and 40 of the exemplary implementation of the current sinking device 36 are p-Channel transistors.
A voltage divider of a clamp circuit, such as the voltage divider 22, generates a bias voltage or a reference voltage, and therefore, is also referred to as a reference voltage generator or a bias voltage generator. As shown in FIG. 2, the simple voltage divider 22 of the prior art is used to reduce the high supply voltage on the node 28 to a smaller voltage on the node 30. For the clamp circuit 20, the major load on the voltage divider 22 is the sub-threshold leakage through the n-channel device 34. For a resistive voltage divider, this load should be small compared to the current consumption of the divider itself in order to maintain good voltage division. This requirement is relaxed in the case of the voltage divider 22, where diode-connected p-channel devices 24 and 26 with non-linear current-voltage characteristics are used instead of resistive elements. Reasonable voltage division can be achieved when the current consumption of the voltage divider 22, defined as the current through device 26 is comparable or even less than the current consumption of a load. Because the device 34 is usually much smaller than the devices 24 and 26, and because the current consumption of the voltage divider 22 is comparable to the leakage through the device 34, the voltage divider 22 can be optimized to consume leakage current that is small compared to the total clamp leakage.
The controller circuit 32 is coupled to a control node of the current sinking device 36 such that the controller circuit 32 couples the control node to a ground potential such that a voltage drop from the control node to the ground potential is less than a threshold voltage of an n-channel transistor, such as the controller transistor 34, during an ESD event on the power supply connection 28. The operation of the controller circuit 32 is explained in further detail in U.S. Pat. No. 5,956,219, which is incorporated herein in its entirety.
One of the problems associated with using the clamp circuit 20 is that the leakage of the voltage divider 22 can only be optimized based on a particular loading condition. Whereas the sub-threshold leakage of the device 34 is a strong function of temperature and other process variation, these changes do not affect the devices in the voltage divider 22 to the same extent. In order to assure satisfactory voltage division across all reasonable usage conditions, the current drive of the voltage divider 22 has to increase to meet the worst case conditions of changes in room temperature, fast process skew, etc. Unfortunately, this may result in significant over-design, which may force current consumption of the voltage divider 22 to become a significant portion of the total clamp leakage under typical operating conditions.
Similarly, it is also desirable to have an improved voltage generation sub-circuit for overall reduction of power consumption of a clamp circuit. A prior art clamp circuit 50 disclosed in FIG. 3 attempts to address this problem by using a low-leakage voltage divider 52 buffered by an analog voltage follower 54 and followed by a controller circuit 56. In the clamp circuit 50, the voltage follower 54 provides low output resistance to drive the leakage through the controller device 56, and furthermore presents only a small load to the voltage divider 52, such that the current consumption of the voltage divider can afford to stay low. Unfortunately, for the voltage follower 54 to work effectively, the input and the output of the voltage follower 54 must differ by one threshold voltage plus an unspecified amount of voltage necessary to turn on one of the transistors in the voltage follower 54. As a result it is difficult to generate highly precise bias voltage using the clamp circuit 50. This is an increasingly important problem with the advances in circuit technology because, as the maximum voltage that transistors in ICs can withstand decreases with each process generation, precision in the voltage reference becomes more critical.
To address the above problems, it is desirable to provide an improved ESD clamp circuit where the internal bias voltage of the clamp tracks the power supply accurately over the entire range of process variations and where the clamp operates with minimal leakage current over a wide range of operating conditions.